Features - Storage Innovations:

INAPAC UNVEILS SOLUTION FOR INTEGRATING DRAM IN SiP APPS

Inapac Technology Inc, a leading semiconductor company exclusively focused on DRAM for system-in-package (SiP) applications, announced a breakthrough solution for integrating DRAM into advanced SiP applications. Using its proprietary wafer stress methodology called voltage induced burn-in emulation (VIBE), Inapac can provide high-performance DRAM dies for stackable and multichip applications. VIBE eliminates the requirement for industry standard, oven-based, burn-in stress testing, ensuring high quality and reliability at the die level, which enables the effective integration of complex DRAM into SiP. Inapac's stackable DRAM technology overcomes the primary barrier for space-efficient, economical SiP solutions in many of today's portable, high bandwidth, and media processing-intensive applications. This innovative new technology has been proven in design wins and through volume shipments to some of the largest semiconductor companies in the world.

To deliver ongoing size reductions while continuing to increase performance and functionality, manufacturers of mobile phones, flat panel displays, hard disk drives, and other electronic products are increasingly considering cost effective and advanced packaging technologies such as SiP, where multiple ICs and other components are integrated into a single package. In memory-intensive applications, integrating DRAM together with other ICs in SiP can significantly reduce footprint, improve signal integrity, reduce power consumption, increase bandwidth, lower cost and improve reliability. However, conventional commodity DRAM often cannot be used for SiP integration, since it requires a post assembly burn-in process of 12-24 hours to reach a suitable quality level. By contrast, Inapac's DRAM dies designed specifically for SiP utilize embedded logic circuitry to ensure testing and quality at the die level without costly burn-in through the use of Inapac's VIBE methodology.

"To meet and exceed the demand for enhanced multimedia functionality such as imaging, video, and 3-D gaming in next generation mobile handsets, we opted to integrate our SoC media processor into a SiP with stacked DRAM to maintain our 10x10mm footprint," said Richard Beriault, director of hardware engineering at Atsana Semiconductor Corp. "Inapac met our needs with DRAM dies that provided for package optimization, SiP testing, quality and reliability, while achieving our overall cost requirements."

"We expect our revolutionary VIBE technology to be rapidly embraced by the industry, because it easily allows our customers to significantly improve the power, performance, and size ratio for their high speed and low power devices," asserted Jean-Pierre Braun, Inapac's president and CEO. "The technical and economic challenges facing the semiconductor industry require an entirely new direction and innovative solution. Our vision and products will help to guide the industry forward in this new direction, allowing even the industry's top players to realize new business opportunities and an even greater potential."

In addition to Atsana Semiconductor, Inapac's technology has also been proven in other SiP applications with major semiconductor manufacturers. The company offers stackable, SiP-optimized DRAM in sizes ranging from 16Mb to 128Mb, in bus widths from 16bits to 128bits, and is available with JEDEC or custom interfaces in high-speed or ultra low-power versions.