Features - Storage Innovations:

RENESAS TECHNOLOGY DEVELOPS 90nm DUAL-PORT SRAM FOR SoC

Renesas Technology Corp announced the development of schemes effective in achieving the world's smallest cell size and lower power consumption in dual-port SRAM (static random access memory) to be used in next-generation microprocessors and SoCs (systems-on-a-chip).

Design and trial production of 90nm (nanometer) technology SRAM using this scheme have confirmed the achievement of the world's smallest memory cell size per bit of 2.04 um2, together with a reduction in standby current of an order of magnitude, to less than one-tenth that of Renesas Technology's current technology, and an approximately two-thirds reduction in operating power per unit frequency.

Background

LSI manufacturing processes have become finer and finer in the pursuit of higher LSI performance and integration levels. One problem that has surfaced as processes become finer is that of gate leakage current due to thinner transistor gate insulation, resulting in increased power consumption while the LSI is in standby mode. There is also a constant trend toward higher operating frequencies in order to achieve higher LSI performance, and higher frequencies are associated with increased operating power. While lowering the power supply voltage is an effective means of reducing leakage current and operating power, simply lowering the voltage also results in a lower maximum LSI operating frequency, preventing the achievement of higher performance.

Meanwhile, amid advances in achieving larger-scale integration, single-port SRAM, in which memory data reads and writes are performed via a single port, is generally the mainstream type of on-chip SRAM. However, for SoCs handling such tasks as image processing and communication processing, there is a growing demand for the use of dual-port SRAM, which speeds up processing by enabling simultaneous accesses from two ports. These kinds of on-chip SRAM have seen a rapid increase in capacity in order to achieve higher LSI performance and functionality, and we can expect to see a steady increase in the proportion of LSI circuitry accounted for on-chip SRAM.

The power consumption of nanometer generation SRAM will thus have a major influence on overall LSI power consumption.

Details Of Technologies

Against this backdrop, Renesas Technology has been conducting research and development in the area of design technologies that enable higher LSI speeds to be achieved together with lower power consumption. Renesas Technology has now developed a scheme for dual-port SRAM that offers higher memory cell density without the addition of complex manufacturing processes. Renesas has also confirmed the efficacy of these developments together with a circuit method that reduces leakage current and operating current while maintaining high speed capability.

The newly developed schemes are as follows:

• Smaller memory cell size through use of new layout structure

  • A new memory cell layout structure has been devised, using a shared contact technique whereby a diffusion section and a polysilicon section for wiring, are connected with a single contact. As a result, a dual-port memory cell has been achieved that has the world's smallest memory cell size per bit of 2.04 um2. Normally, the cell size of dual-port SRAM is at least twice that of single-port SRAM of the same design rule, but this technique has produced a cell area only approximately 1.6 times as large. In addition, the structure provides fully shielded bit lines, making it possible to reduce interference noise due to electrical signal interactions between adjacent wires.

• Dynamic "column bias control method" for memory cell array

  • The previous mainstream method for reducing leakage current has been performing voltage control in block units or in row direction of the memory cell array. Now, a "column voltage control method" has been developed that enables not only leakage current but also the operating current to be reduced by performing column direction voltage control. Details are as follows:

    • GND (ground) lines of the memory cell array are normally fixed at 0 V, but these GND lines are subjected to dynamic voltage control in column units.

    • Setting the GND lines to a voltage of approximately 0.4 V lowers the gate leakage current, enabling the overall memory cell standby current to be reduced.

    • When a memory cell is accessed, only the selected column GND line voltage is made 0 V, setting an operational state, while other column GND lines are kept at a voltage of approximately 0.4 V.

    • This voltage variation is controlled dynamically in memory cell column units according to whether or not access is performed.

By making the memory cell array operating area only columns that are accessed, it has become possible to reduce not only the standby current but also the operating current.

Effects

A 64Kb (32-Kbyte x 2) dual-port SRAM test chip was created using a 90 nm CMOS process, and the effects of the above-described schemes were investigated. The following results were confirmed based on a comparison with SRAM employing conventional technology.

The integration density was improved by approximately 25 percent, attaining 310 Kb/mm2. With a 1.2 V power supply voltage at room temperature, a standby leakage current of 0.45 uA was achieved, a reduction of more than 90 percent.

Power consumption per unit frequency during operation was 0.07 mW/MHz, an approximately 64 percent reduction.