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MoSys Ports 1T-SRAM-Q To NEC Electronics 90nm Logic Process

MoSys Inc, a leading provider of high density SoC embedded memory solutions, announced the initial silicon verification of MoSys' 1T-SRAM-R memory technology on NEC Electronics' 90-nanometer standard logic process. Silicon testchips for MoSys' quad density 1T-SRAM-Q embedded memory technology are also currently being manufactured on NEC Electronics' 90-nanometer logic process. This represents the latest milestone in a successful relationship between the companies on multiple process generations and memory technologies starting in 1999.

"Today's system level LSI designers need to efficiently embed more and more memory in their designs to reach the difficult performance and power requirements demanded by their markets," said Hirokazu Hashimoto, executive vice president at NEC Electronics Corporation, "We are very pleased to reach this new milestone in our cooperation with MoSys to bring its latest embedded memory technologies to our SoC customers."

"MoSys has already very successfully partnered with NEC Electronics to deliver leading-edge SoC embedded memory solutions in high volume," commented Mark-Eric Jones, vice president and general manager of Intellectual Property at MoSys "We look forward to continuing and broadening this relationship to enable NEC Electronics' 90-nanometer logic process customers to take advantage of our latest 1T-SRAM-Q and 1T-SRAM-R technologies for their SoC designs."