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Agere SerDes Core Delivers 1 Through 10 Gb/s Performance
Agere Systems became the first company to announce that it is providing an advanced serializer/deserializer (SerDes) core that can address all the necessary high-speed input/output protocols for storage area networking (SAN) infrastructure equipment on a single chip. Agere's new SDM4G13 SerDes core is being designed into ASICs using TSMC's 130-nanometer process technology.
Agere's breakthrough SerDes addresses the immediate market opportunity for 1, 2 and 4 gigabits per second Fibre Channel while offering customers an easy evolution to 10 gigabits per second all in the same core. The new SerDes core also supports 1.5 and 3 gigabits per second serial ATA (SATA) and serial attached SCSI (SAS) and PCI Express standards for high-speed serial storage interconnects. This integration allows systems designers the flexibility of being able to design chips for storage networking systems using any speed and any protocol. Agere's solution also provides the added advantage of being able to reuse the SerDes intellectual property in multiple chips and multiple systems, saving time and money in the design process.
"The integration of SerDes technology will continue to be a popular design trend going forward, especially as SAN disk array and infrastructure OEMs look to reduce real estate, lower power and reduce costs," said Sean Lavey, an analyst at IDC. "Having a SerDes core that can provide a broad variety of necessary speeds and protocols all on one device is a significant step in providing the capabilities SAN providers need to quickly and affordably roll out their next-generation systems."
Agere has one of the broadest portfolios of SerDes and high-speed interface technology in the industry. Agere's interface portfolio supports speeds from 155 megabits per second to 10 gigabits per second and offers integration into systems on a chip (SoCs) compliant with standards including 1, 2 and 4 Gigabit Fibre Channel, 1.5 and 3 gigabits per second SATA and SAS, SCSI, PCI, PCI-X, PCI-X 2.0, PCI Express, SPI-3/4/5, SFI-4, serial RapidIO and XAUI. Agere designs its SerDes to perform better than industry specifications in areas such as jitter performance.
"Agere's experience in integrating high-speed interface technology and our advanced signal integrity tools allow us to deliver high-performance SoCs to customers on the first pass," said Necip Sayiner, vice president of Agere's Networking ICs business unit. "Our single-chip SoC solutions allow SAN customers to get to market faster with a higher quality product that consumes less power and provides a lower total cost of ownership."
SAN Market Embracing Fibre Channel Technology
Industry analyst firm IDC expects the worldwide enterprise storage connect semiconductor market to grow at a compound annual growth rate of 15 percent between 2002 and 2007 and the Fibre Channel infrastructure market to grow at a CAGR of 30 percent during the same timeframe.
Today, SAN equipment providers are rapidly adopting 4 gigabits per second Fibre Channel technology. As corporate users drive more transactions, digital photographs, voice files and video files across networks, SAN architects are asking for 4 gigabits per second storage systems, fabric switches and host bus adapters (HBAs) that cost about the same as similar 2 gigabits per second products and that are 100 percent compatible with installed 1 gigabits per second and 2 gigabits per second products.
For applications that stream large amounts of data across a fabric such as inter-switch links, voice and video, 4 gigabits per second products will double current Fibre Channel performance at about the same price as 2 gigabits per second Fibre Channel, while maintaining backward compatibility with 1 gigabits per second and 2 gigabits per second servers, networks and storage.
"We've engineered our SerDes core in ways that bring tremendous benefit to our ASIC customers," Sayiner said. "As Fibre Channel SAN markets continue to evolve, Agere's SerDes offers our SAN customers the industry's only backwardcompatible and future-proof technology to accommodate any protocol and any speed from 1-to-10 gigabits per second."
Designed to Exceed Specifications
Agere tests SerDes circuits at full speed, which provides an assurance of quality because customers know the SerDes works before the chip goes to packaging. This also helps provide first-pass success on new ASIC designs. The company works closely with its customers by helping design the chip and the circuit board to maximize throughput and signal integrity throughout the system. Modeling how the SerDes is interconnected inside the chip helps provide higher levels of signal integrity. The SerDes and ASIC package are co-designed to provide the highest quality of signal integrity at the package pin.
Agere's SerDes core, a high-speed silicon interconnect macrocell, is integrated in Agere ASIC system chips, standard product systems-on-a-chip, and standalone SerDes/bridge devices. A SerDes core performs input and output functions that increase and decrease the transmission speed and reception of voice, data and video signals through copper and fiber optic cables. SerDes cores are used widely in many types of data communications, data storage and telecommunications equipment.
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